library   ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;

entity money is
  port(dissin,disten:in std_logic_vector(3 downto 0);
		 timsin,timten:in std_logic_vector(3 downto 0);
       num,num1:out std_logic_vector(3 downto 0));
  end;

architecture rtl of money is
  begin
    process(dissin,disten,timsin,timten)
     variable timeX,distence: integer;
	  variable res: integer;
      begin
			
			timeX := 10 * conv_integer(timten) + conv_integer(timsin);
			distence := 10 * conv_integer(disten) + conv_integer(dissin);
			res := timeX / 2 + distence;
			
			num1 <= CONV_STD_LOGIC_VECTOR(res/10,4);
			num <= CONV_STD_LOGIC_VECTOR(res mod 10,4);

			
    end process;
  end;
  
    --data1 wei high